1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to configuring logic blocks of programmable logic devices.
2. Description of the Related Art
Programmable logic devices (PLD's) such as field programmable gate arrays (FPGA's) can include an assortment of different types of components such as memories, central processing units, and the like. Increasingly, “black boxes”, also referred to as logic blocks, have been introduced into these devices to enhance application specific performance. One type of “black box” is, for example, a digital signal processor (DSP) block. Traditionally, logic block performance, and particularly DSP block performance, has been optimized during the synthesis phase of circuit design. During synthesis, a Hardware Description Language (HDL) design definition of a circuit is processed to generate the logical or physical representation of the circuit design for the targeted PLD.
When implementing a circuit design using a PLD, behavioral HDL traditionally has been mapped onto logic blocks of the target device. In illustration, Xilinx, Inc. of San Jose, Calif. manufactures various PLD's such as the Xilinx® Virtex4 family of FPGA's. These devices provide a plurality of different configurable logic blocks as described above. One particular type of logic block available on Virtex4 devices is the DSP48 block. This type of logic block provides standardized DSP functions and is highly configurable. A DSP48 block combines an 18-bit by 18-bit signed multiplier with a 48-bit adder and a programmable multiplexer which allows input to be selected for the adder. A description is disclosed in the XtremeDSP Design Considerations User Guide, UG073 (v1.2) Feb. 4, 2005 from Xilinx, Inc., pages 1-54, which is herein incorporated by reference.
Other aspects of a DSP48 block can be selected as well. For example, one group of parameter settings indicates whether ports of the logic block are registered and the amount of pipelining used for a given port. That is, input ports, output ports, and certain internal logic of the DSP48 block can be registered with varying amounts of pipelining being applied to each. More particularly, optional input, output, and multiplier pipeline registers can be selectively configured for a given circuit design.
Like other types of logic blocks, each DSP48 block usually is configured by mapping behavioral HDL onto the logic block. Determinations as to whether a port is registered and the amount of pipelining used for a given port are made during the synthesis phase of circuit design. During synthesis, however, accurate signal delay and block delay information has not yet been determined. In consequence, the configuration of logic blocks is not timing driven. Without the availability of timing information, configuration and/or optimization of logic blocks, and particularly DSP blocks, can be difficult.
It would be beneficial to provide a technique for optimizing logic blocks, including DSP blocks, of a PLD which overcomes the limitations described above.